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​​​​​​​SystemC/TLM2 Primer
This 3-day training introduces the SystemC C++ class library and the TLM 2.0 modeling standard. It is intended for engineers who are new to SystemC or those with an interest in learning SystemC for modeling purposes. The participants will learn how to write, compile, execute and debug system and hardware descriptions with SystemC and will receive thorough coverage of the concepts of the Accellera/IEEE TLM 2.0 modeling standard. This course is a mix of lectures and exercises.
You can also book this seminar as an in-house seminar! Just write us a short non-binding e-mail with the desired date and location as well as the number of participants: training@eclipseina.com
Get an overview of all our seminars on embedded-academy.com!
Target Group
Developers in the area of HW/SW co-design
Prerequisites
Fundamental C/C++, SystemC and TLM2 knowledge is a prerequisite.
A laptop with permissions to install software is required.
Training Content
Introduction to SystemC
- Core library basics
- Modules& communication (channels, ports, and exports)
- Simulation kernel: scheduler, events, and event queues
- Modeling behavior
- Method processes
- Dynamic and static thread processes
- Hierarchy creation and Simulation semantics
- Core library elements
- SystemC data types
- Debugging and tracing aids
- Primitive channels
- User defined channels
- Custom constructors
Introduction to the IEEE TLM 2.0 Standard
- TLM 2.0 Overview
- Interfaces, sockets, generic payload, and protocol
- Generic payload overview
- Interfaces
- Transport (blocking interface and non-blocking)
- DMI
- Debug
- Sockets
- Initiator and Target
- Socket Binding
- Hierarchy, Multi-connect
- Convenience Sockets
- Simple Sockets
- Tagged Sockets and multi-passthrough Sockets
- Generic Payload In-depth
- Byte Enable, Streaming, and endianness
- Memory Management
- Generic Payload Extensions (and exercise)
SystemC based Standards and Libraries
- SystemC Verification Library
- Control and Configuration Interface (CCI) for SystemC
- SystemC Unified Verification Methodology (SystemC UVM)
Organiser:
Eclipseina GmbH | Embedded Academy
Technologiezentrum TechBase
Franz-Mayer-Straße 1
93053 Regensburg
Tel.: +49 941 / 462 974 20
Veranstaltungsort
Technologiezentrum TechBaseEclipseina GmbH im 1. Stock
Franz-Mayer-Straße 1
93053 Regensburg | 09:00 - 17:00
Deutschland
Koordinaten (Lat, Long):
49.002216, 12.100555
Karte anzeigenRoutenplanung